1. Field of the Invention
The present invention generally relates to a memory controller for controlling a burst-accessible external memory device. More particularly, the present invention relates to a memory controller for controlling an external memory device to be accessible even in an addressing mode that is not supported by the external memory device.
2. Description of the Background Art
With recent increase in operation speed of the processors mounted in the information processing units like personal computers and the electrical household appliances, fast access is increasingly required for the memories mounted in these apparatuses. Therefore, burst-accessible memories such as flash memory and ROM (Read Only Memory) are now increasingly developed.
FIG. 1 is a block diagram showing an exemplary structure of a burst-accessible external memory device 100. This external memory device 100 includes a cell matrix 101, a burst control circuit 102 for controlling addressing in burst access, an address incrementer 103 for generating an address in burst access, an address latch/decoder 104 for latching and decoding an external address or an address generated by the address incrementer 103, a data latch 105 for latching the data that is output from the cell matrix 101 according to the decode result of the address latch/decoder 104, an input/output (I/O) buffer 106 for receiving the external data and outputting the latched data in the data latch 105, and a control circuit 107 for controlling data input/output and the like.
The external memory device 100 receives signals XCS#, XRS#, XWS#, XAB[8:30], CLK and XADV# from a memory controller described below. The signal XCS# is a chip select signal for making the operation of each unit within the external memory device 100 valid. The signal XRS# is a read strobe signal indicating a data output period in read access. The signal XWS# is a write strobe signal indicating a write access period.
XAB [8:30] indicates an address bus for addressing the external memory device 100 to be accessed. XAB[8:30] refers to 23 bits of the address bus XAB8 to XAB30. Of XAB8 to XAB30, XAB8 represents the most significant bit, and XAB30 represents the least significant bit.
The signal CLK is a clock signal for use within the external memory device 100 in order to generate an address in burst access. The signal XADV# is an address valid signal for receiving and latching the address on XAB[8:30] into the external memory device 100.
XDB[0:15] indicates an external data bus for data input/output. XDB[0:15] refers to 16 bits of the data bus XDB0 to XDB15. Of XDB0 to XDB15, XDB0 represents the most significant bit, and XDB15 represents the least significant bit.
In the single access mode, the address latch/decoder 104 receives and latches an address on XAB[8:30] in response to assertion of the signal XADV#. The address latch/decoder 104 then decodes that address for output to the cell matrix 101. The cell matrix 101 selects a memory cell according to the decode result, and output the data to the data latch 105.
In the burst access mode, the address incrementer 103 fetches an address on XAB[8:30] in response to assertion of the signal XADV# in the first access. The address latch/decoder 104 receives the address that is output from the address incrementer 103. The address latch/decoder 104 then decodes that address for output to the cell matrix 101. The cell matrix 101 selects a memory cell according to the decode result, and output the data to the data latch 105.
In the second and following accesses, the address incrementer 103 increments the address in synchronization with the signal CLK for output to the address latch/decoder 104. The address latch/decoder 104 receives the address that is output from the address incrementer 103. The address latch/decoder 104 then decodes that address for output to the cell matrix 101. The cell matrix 101 selects a memory cell according to the decode result, and output the data to the data latch 105.
The operation of the address incrementer 103 varies depending on an addressing mode supported by the external memory device 100. Such addressing modes include: a Wrap mode that implements wraparound access capable of accessing only within a page boundary; and a Non-Wrap mode capable of accessing successive addresses regardless of the page boundary.
For example, in the case where the burst length is four words (16 bits/word), the lower address value that is output from the address incrementer 103 varies in the following manner in each of the addressing modes. Note that the starting address is 2.
Wrap mode: 2xe2x86x923xe2x86x920xe2x86x921
Non-Wrap mode: 2xe2x86x923xe2x86x924xe2x86x925
The control circuit 107 receives the signals XCS#, XRS# and XWS# from the memory controller, and generates a timing signal of the address latch/decoder 104, data latch 105 and I/O buffer 106.
FIG. 2 is a block diagram schematically showing the structure of the conventional memory controller for controlling the external memory device 100 of FIG. 1. This memory controller 200 includes a state machine 201 for causing state transition according to the operation mode of the external memory device 100, a wait setting register 202 in which is set the number of waits in accessing the external memory device 100 by a not-shown microprocessor or the like, a wait counter 203 for counting the number of waits that is set in the wait setting register 202, a burst counter 204 for counting the number of accesses in the burst access mode, a control signal generation circuit 205 for generating a control signal for controlling the external memory device 100 and a bus controller 300 according to the state of the state machine 201, and an address latch 206 for latching an address from the bus controller 300 for output to the external memory device 100.
The memory controller 200 receives signals EIHREQ, EIHBURST, EIHBCNT[0:2] and EIHAB[8:30] from the bus controller 300. The signal EIHREQ is a signal indicating an access request to an external bus from the bus controller 300. The external bus herein refers to a bus connected to the right side of the memory controller 200. The external memory device 100 and the like are connected to the external bus. An internal bus herein refers to a bus connected to the left side of the memory controller 200.
The signal EIHBURST is a signal indicating whether the access to the external memory device 100 is burst access or not. The signal EIHBCNT[0:2] is a signal indicating the burst length in burst access. EIHAB[8:30] indicates an internal address bus on which the address for access to the external bus (access to the external memory device 100 or the like) is output.
The state machine 201 causes state transition in each operation mode with reference to the signals EIHREQ and EIHBURST, a signal WCOUNT from the wait counter 203, and a signal BCOUNT from the burst counter 204. State transition of the state machine 201 will be described later.
The control signal generation circuit 205 generates signals CSHACK, CSHEVLD and CSHXVLD according to the state of the state machine 201 for output to the bus controller 300. The signal CSHACK is a signal for notifying the bus controller 300 of acknowledgement of the access request by the signal EIHREQ from the bus controller 300. The signal CSHXVLD is a signal indicating whether the data on the external data bus (XDB[0:15]) is valid or not. The signal CSHEVLD is a signal indicating whether the data on the internal data bus (EIHDB[0:15]) is valid or not.
The control signal generation circuit 205 generates the signals XCS#, XRS#, XWS# and XADV# (which are defined above) according to the state of the state machine 201 for output to the external memory device 100.
The wait counter 203 counts the number of waits in accessing to the external memory device 100 with reference to the number of waits that is set in the wait setting register 202. The burst counter 204 receives the value of the signal EIHBCNT[0:2] as an initial value at the start of burst access, and counts the number of accesses to the external memory device 100. The address latch 206 receives and latches an address that is output from the bus controller 300 onto EIHAB[8:30], and outputs that address onto XAB[8:30].
The memory controller 200 has two operation modes: a single access mode and a burst access mode. In the single access mode, the memory controller 200 executes a single access to the external memory device 100 in response to each access request. In the burst access mode, the memory controller 200 successively executes a plurality of accesses to the external memory device 100 in response to each access request, allowing for fast access. When the signals EIHREQ and EIHBURST are both asserted simultaneously, the memory controller 200 determines that the operation mode is the burst access mode, and operates in the burst access mode. When only the signal EIHREQ is asserted, the memory controller 200 determines that the operation mode is the single access mode, and operates in the single access mode.
(1) Single Access Mode
FIG. 3 is a diagram showing the state transition of the memory controller 200 in the single access mode. Note that the state transition of the state machine 201 occurs in synchronization with the signal CLK.
The state machine 201 is in the IDLE state when being ready to accept an access request from the bus controller 300. When only the signal EIHREQ is asserted (EIHREQ=1, EIHBURST=0), the state machine 201 transitions to the START state. The START state corresponds to a cycle in which assertion of the signal XCS# is started. One cycle of the START state is always inserted for every access request.
If the count value WCOUNT of the wait counter 203 is not xe2x80x9c0xe2x80x9d (WCOUNTxe2x89xa00), the state machine 201 transitions to the WAIT state in the following cycle. The WAIT state is repeated until WCOUNT becomes xe2x80x9c0xe2x80x9d. In other words, as many access waits as the number of waits in the wait setting register 202 are inserted.
When WCOUNT is xe2x80x9c0xe2x80x9d in the START state, or when WCOUNT is xe2x80x9c0xe2x80x9d in the WAIT state, the state machine 201 transitions to the END state in the following cycle. The END state is a cycle in which bus access is terminated. One cycle of the END state is always inserted at the end of the bus access. In this cycle, the data on XDB[0:15] is rendered valid, whereby the access to the external memory device 100 is completed. The state machine 201 transitions to the IDLE state in the following cycle. The IDLE state is repeated until another access request is output from the bus controller 300.
FIG. 4 is a timing chart illustrating the operation of the memory controller 200 in the single access mode. This timing chart indicates a read operation, and the number of access waits is two cycles.
If the bus controller 300 asserts the signal EIHREQ while the state machine 201 is in the IDLE state (C2), the control signal generation circuit 205 asserts the signal CSHACK in this cycle in order to notify the bus controller 300 of acknowledgement of the access request.
The state machine 201 then transitions to the START state (C3), and the control signal generation circuit 205 responsively starts asserting the signals XCS# and XRS#. In this cycle, the address latch 206 receives an address that is output onto EIHAB[8:30]. The address latch 206 outputs that address onto XAB[8:30], and the control signal generation circuit 205 asserts the signal XADV#. The wait counter 203 receives the number of waits that is set in the wait setting register 202.
The wait counter 203 starts down-counting as soon as the state machine 201 transitions to the WAIT state in the following cycle (C4). As many wait cycles (C4, C5) as the number of waits in the wait setting register 202 are inserted.
The state machine 201 transitions to the END state in the following cycle (C6). In this cycle, the control signal generation circuit 205 asserts the signal CSHXVLD in order to notify the bus controller 300 that the data output onto XDB[0:15] is valid.
In response to the notification from the memory controller 200, the bus controller 300 receives the data on XDB[0:15] in the following cycle (C7) for output onto EIHDB[0:15]. In this cycle, the control signal generation circuit 205 asserts the signal CSHEVLD in order to notify the bus controller 300 that the data output onto EIHDB[0:15] is valid. In this cycle, the control signal generation circuit 205 negates the signals XCS# and XRS#, thereby completing the access to the external memory device 100. Note that the count value BCOUNT of the burst counter 204 is not used in the single access mode.
(2) Burst Access Mode
FIG. 5 is a diagram showing the state transition of the memory controller 200 in the burst access mode. When the signals EIHREQ and EIHBURST are asserted in the IDLE state (EIHREQ=1, EIHBURST=1), the state machine 201 transitions to the START state. The START state corresponds to a cycle in which assertion of the signal XCS# is started. One cycle of the START state is always inserted for every access request.
If the count value WCOUNT of the wait counter 203 is not xe2x80x9c0xe2x80x9d (WCOUNTxe2x89xa00), the state machine 201 transitions to the WAIT state in the following cycle. The WAIT state is repeated until WCOUNT becomes xe2x80x9c0xe2x80x9d. In other words, as many access waits as the number of waits in the wait setting register 202 are inserted.
When BCOUNT is xe2x80x9c0xe2x80x9d (BCOUNT=0) in the START state, the state machine 201 transitions to the END state in the following cycle.
When WCOUNT is xe2x80x9c0xe2x80x9d (WCOUNT=0) in the START state or when WCOUNT is xe2x80x9c0xe2x80x9d and BCOUNT is not xe2x80x9c0xe2x80x9d (WCOUNT=0, BCOUNTxe2x89xa00) in the WAIT state, the state machine 201 transitions to the BURST state in the following cycle. The BURST state is repeated until BCOUNT becomes xe2x80x9c0xe2x80x9d. In other words, the BURST state is repeated as much as the burst length of the signal EIHBCNT[0:2]. In the BURST state, successive addresses of the external memory device 100 are accessed in synchronization with the signal CLK.
When WCOUNT and BCOUNT are xe2x80x9c0xe2x80x9d (WCOUNT=0, BCOUNT=0) in the WAIT state, or when BCOUNT is xe2x80x9c0xe2x80x9d (BCOUNT=0) in the BURST state, the state machine 201 transitions to the END state. The END state is a cycle in which bus access is terminated. One cycle of the END state is always inserted at the end of the bus access. Burst access to the external memory device 100 is thus completed in this cycle. The state machine 201 transitions to the IDLE state in the following cycle. The IDLE state is repeated until another access request is output from the bus controller 300.
FIG. 6 is a timing chart illustrating the operation of the memory controller 200 in the burst access mode. This timing chart indicates a read operation, wherein the number of access waits is two cycles, and the burst length is four words.
If the bus controller 300 asserts the signals EIHREQ and EIHBURST simultaneously while the state machine 201 is in the IDLE state (C2), the state machine 201 determines that the request is a burst access request, and sets the operation mode to the burst access mode. The control signal generation circuit 205 asserts the signal CSHACK in this cycle in order to notify the bus controller 300 of acknowledgement of the access request. In the case of the burst access request, the signals EIHREQ and EIHBURST are kept asserted until burst access is completed.
The state machine 201 then transitions to the START state (C3), and the control signal generation circuit 205 responsively starts asserting the signals XCS# and XRS#. In this cycle, the address latch 206 receives an address that is output onto EIHAB[8:30]. The address latch 206 outputs that address onto XAB[8:30], and the control signal generation circuit 205 asserts the signal XADV#. The wait counter 203 receives the number of waits that is set in the wait setting register 202. The burst counter 204 receives the burst length of the signal EIHBCNT[0:2]. Note that the burst length of the signal EIHBCNT[0:2] is (an expected burst length xe2x88x921).
The wait counter 203 starts down-counting as soon as the state machine 201 transitions to the WAIT state in the following cycle (C4). As many wait cycles (C4, C5) as the number of waits in the wait setting register 202 are inserted.
The burst counter 204 starts down-counting as soon as the state machine 201 transitions to the BURST state in the following cycle (C6). In this cycle, the control signal generation circuit 205 asserts the signal CSHXVLD in order to notify the bus controller 300 that the data output onto XDB[0:15] is valid.
In response to the notification from the memory controller 200, the bus controller 300 receives the data on XDB[0:15] in the following cycle (C7) for output onto EIHDB[0:15]. In this cycle, the control signal generation circuit 205 asserts the signal CSHEVLD in order to notify the bus controller 300 that the data output onto EIHDB[0:15] is valid.
In the cycles C7 and C8, the control signal generation circuit 205 retains the values of the signals XCS# and XRS#, thereby allowing the external memory device 100 to access to successive addresses.
The state machine 201 transitions to the END state in the following cycle (C9).
The state machine 201 transitions to the IDLE state in the following cycle (C10). In this cycle, the control signal generation circuit 205 negates the signals XCS# and XRS#, thereby completing the burst access to the external memory device 100. The control signal generation circuit 205 also negates the signal CSHXVLD in this cycle.
In the following cycle (C11), the control signal generation circuit 205 negates the signal CSHEVLD in order to notify the bus controller 300 that the data on EIHDB[0:15] is no longer valid.
As described above, the external memory device 100 includes the address incrementer 103 therein, allowing for fast access to successive addresses in synchronization with a clock signal.
However, some external memory devices support either the Wrap mode or Non-Wrap mode, or have a different burst length. If the memory controller 200 conducts burst access in an addressing mode or with a burst length that is not supported by the external memory device 100, a desired address is not accessed, causing malfunction of the microprocessor or erroneous data processing due to the wrong data being read.
It is an object of the invention to provide a memory controller that enables a bus controller to read the correct data even when an access request from the bus controller corresponds to an access mode that is not supported by an external memory device.
It is another object of the invention to provide a memory controller that enables a bus controller to rapidly read the correct data even when an access request from the bus controller corresponds to an access mode that is not supported by an external memory device.
According to one aspect of the invention, a memory controller for controlling access to a burst-accessible memory according to an access request from a bus controller includes: a detection circuit for detecting that a burst access request from the bus controller corresponds to an access mode that is not supported by the memory; and a control circuit for accessing the memory in an access mode different from that of the burst access request from the bus controller according to the detection result of the detection circuit, and controlling data output so that data is output to the bus controller in an order corresponding to the burst access request.
The control circuit accesses the memory in an access mode different from that of the burst access request from the bus controller, and controls data output so that the data is output to the bus controller in the order corresponding to the burst access request. This enables the bus controller to read the correct data according to the burst access request.
According to another aspect of the invention, a memory control method for controlling access to a burst-accessible memory according to an access request from a bus controller includes the steps of: detecting that a burst access request from the bus controller corresponds to an access mode that is not supported by the memory; and accessing the memory in an access mode different from that of the burst access request from the bus controller according to the detection result, and controlling data output so that data is output to the bus controller in an order corresponding to the burst access request.
The memory is accessed in an access mode different from that of the burst access request from the bus controller, and data output is controlled so that the data is output to the bus controller in the order corresponding to the burst access request. This enables the bus controller to read the correct data according to the burst access request.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.